{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,5,5]],"date-time":"2022-05-05T22:40:24Z","timestamp":1651790424327},"reference-count":9,"publisher":"IGI Global","issue":"3","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,7]]},"abstract":"<jats:p>The supercomputing platform is suitable for the acceleration of high throughput computing intensive applications, due to the difficulty of mathematical calculation and the communication of multi-user large data volumes, the throughput rate requirement of computing equipment in various cipher processing related applications is very high. In order to accelerate the operation of the application of high throughput cipher processing, this article proposes a coarse-grained parallel acceleration framework for MIC of supercomputing platform. The framework does not take the computing process of the algorithm into account, but achieves parallel computing by assigning the data to each computing node. The framework adopts a three-level parallel structure to accelerate the application of cipher processing, namely multi-node, multi-MIC of nodes, and multi-thread of MICs. The experimental results for a variety of cipher processing applications show that the framework applies coarse-grained parallel processing to the applications of high throughput cipher processing by supercomputing platform, and obtains the significant acceleration effect.<\/jats:p>","DOI":"10.4018\/ijitn.2019070102","type":"journal-article","created":{"date-parts":[[2019,4,29]],"date-time":"2019-04-29T18:44:27Z","timestamp":1556563467000},"page":"11-22","source":"Crossref","is-referenced-by-count":0,"title":["Accelerating High Throughput Cipher Processing on Supercomputing Platform"],"prefix":"10.4018","volume":"11","author":[{"given":"Hao","family":"Wang","sequence":"first","affiliation":[{"name":"National Laboratory for Parallel and Distributed Processing, National University of Defense Technology, Changsha, China"}]},{"given":"Jingfei","family":"Jiang","sequence":"additional","affiliation":[{"name":"National Laboratory for Parallel and Distributed Processing, National University of Defense Technology, Changsha, China"}]}],"member":"2432","reference":[{"key":"IJITN.2019070102-0","author":"J.Chai","year":"2014","journal-title":"Research on key Technologies of Large Scale Parallel Computing for Accelerator-based Heterogeneous Systems for Applications"},{"key":"IJITN.2019070102-1","article-title":"FPGA implementation of AES encryption and decryption.","author":"A. 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