{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,10]],"date-time":"2026-06-10T16:32:55Z","timestamp":1781109175255,"version":"3.54.1"},"reference-count":25,"publisher":"IGI Global Scientific Publishing","issue":"3","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,7,1]]},"abstract":"<p>This article describes how nowadays, data is widely transmitted over the internet in the real time. Wherever the transmission or storage is required, security is needed. High speed processing hardware machine with reduced complexity are used for the security of the data, that are transmitted in real time. The information which is to be secure are encoded by pseudorandom key. Chaotic numbers are used in place of a pseudorandom key. The generated chaotic values are analogous in nature, these analog values are digitized to generate encryption key like 8-bit, 16-bit, 32-bit. To generate an 8-bit key, an 8-bit quantizer is required. The design of 8-bit quantizer requires 256 levels which needs lot of complex hardware to implement. In this article, an 8-bit quantizer is designed with reduced complexity, where hardware requirement is reduced by more than 12 times. Without compromising the randomness of the sequence generated. To increase the randomness and confusion timed hop random selection is used. The randomness of the sequence generated by the chaotic generators is analyzed by NIST test suite, to test for its randomness.<\/p>","DOI":"10.4018\/ijrsda.2018070104","type":"journal-article","created":{"date-parts":[[2018,5,30]],"date-time":"2018-05-30T07:48:39Z","timestamp":1527666519000},"page":"55-70","source":"Crossref","is-referenced-by-count":0,"title":["8-Bit Quantizer for Chaotic Generator With Reduced Hardware Complexity"],"prefix":"10.4018","volume":"5","author":[{"family":"Zamarrud","sequence":"first","affiliation":[{"name":"Z.H.C.E.T, A.M.U, Aligarh, India"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Muhammed","family":"Izharuddin","sequence":"additional","affiliation":[{"name":"Z.H.C.E.T, A.M.U, Aligarh, India"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"2432","reference":[{"key":"IJRSDA.2018070104-0","doi-asserted-by":"publisher","DOI":"10.1109\/MSPCT.2011.6150443"},{"key":"IJRSDA.2018070104-1","doi-asserted-by":"crossref","unstructured":"Al-Shameri, W. F. H., & Mahiub, M. A. (2013). Some Dynamical Properties of the Family of Tent Maps. International Journal of Math. Analysis, 7(29), 1433 - 1449.","DOI":"10.12988\/ijma.2013.3361"},{"key":"IJRSDA.2018070104-2","unstructured":"Bonde, V., & Kale, A. (2013). A Review on Implementation of Random Number Generation based on FPGA. International Journal of Science and Research (IJSR)."},{"key":"IJRSDA.2018070104-3","doi-asserted-by":"publisher","DOI":"10.1109\/ISPCC.2012.6224348"},{"key":"IJRSDA.2018070104-4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCSEE.2012.193"},{"key":"IJRSDA.2018070104-5","doi-asserted-by":"publisher","DOI":"10.1109\/SSST.2012.6195137"},{"key":"IJRSDA.2018070104-6","article-title":"FPGA implementation of chaotic pseudo-random bit generators.","author":"P.Dabal","year":"2012","journal-title":"19th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES)"},{"issue":"5","key":"IJRSDA.2018070104-7","first-page":"325","article-title":"A Cryptography Algorithm Using the Operations of Genetic Algorithm & Pseudo Random Sequence Generating Functions.","volume":"3","author":"S.Dutta","year":"2014","journal-title":"International Journal of Advances in Computer Science and Technology"},{"key":"IJRSDA.2018070104-8","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-48797-6_4"},{"key":"IJRSDA.2018070104-9","doi-asserted-by":"publisher","DOI":"10.1145\/2905055.2905281"},{"key":"IJRSDA.2018070104-10","author":"F.Khani","year":"2013","journal-title":"Digital realization of twisted tent map and ship map with LFSR as a pseudo-chaos generator. In 3th International eConference on Computer and Knowledge Engineering (ICCKE)"},{"key":"IJRSDA.2018070104-11","article-title":"FPGA Implementation of 8, 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial using VHDL.","author":"A. P.Kumar","year":"2012","journal-title":"International Conference on Communication Systems and Network Technologies (CSNT)"},{"key":"IJRSDA.2018070104-12","doi-asserted-by":"crossref","unstructured":"Merah, L., Ali-Pacha, A., Said, N. H., & Mamat, M. (2013). A Pseudo Random Number Generator Based on the Chaotic System of Chua\u2019s Circuit, and its Real Time FPGA Implementation. Applied Mathematical Sciences, 7(55), 2719-2734.","DOI":"10.12988\/ams.2013.13242"},{"issue":"2","key":"IJRSDA.2018070104-13","first-page":"189","article-title":"Review on Chaotic Sequences Based Cryptography and Cryptanalysis.","volume":"3","author":"M.Mishra","year":"2011","journal-title":"International Journal of Electronics Engineering"},{"key":"IJRSDA.2018070104-14","unstructured":"Mishra, S., Srivastava, R., & Tiwari, A. (2015). Enhance the Performance of Chaotic Generator in the Filed of Cryptography: A Secret Key Generation Approach. Global Journal of Computer Science and Technology Neural & Artificial Intelligence, 15(1)."},{"issue":"1","key":"IJRSDA.2018070104-15","first-page":"12","article-title":"VHDL implementation for a pseudo random number generator based on tent map.","volume":"1","author":"F.Ricardo","year":"2015","journal-title":"Computational and Applied Mathematics Computational and Applied Mathematics"},{"key":"IJRSDA.2018070104-16","doi-asserted-by":"publisher","DOI":"10.1109\/ICAES.2013.6659376"},{"key":"IJRSDA.2018070104-17","article-title":"Security threats in cloud computing.","author":"F. B.Shaikh","year":"2011","journal-title":"International Conference for Internet Technology and Secured Transactions (ICITST)"},{"key":"IJRSDA.2018070104-18","doi-asserted-by":"publisher","DOI":"10.1109\/ECS.2014.6892516"},{"key":"IJRSDA.2018070104-19","doi-asserted-by":"crossref","unstructured":"Swami, D. S., & Sarma, K. K. (2014). A chaos based pn sequence generator for direct-sequence spread spectrum communication system. International Journal Of Circuits, Systems And Signal Processing, 8.","DOI":"10.1109\/SPIN.2014.6777060"},{"key":"IJRSDA.2018070104-20","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.25"},{"key":"IJRSDA.2018070104-21","unstructured":"Vlad, A., Luca, A., Hodea, O., & Tataru, R. (2013). Generating chaotic secure sequences using tent map and a running-key approach. Proceedings Of The Romanian Academy, 14(A), 295-302."},{"key":"IJRSDA.2018070104-22","article-title":"Design of a Generalized Bidirectional Tent Map Suitable for Encryption Applications.","author":"S. S.Wafaa","year":"2015","journal-title":"11th International Computer Engineering Conference(ICENCO)"},{"key":"IJRSDA.2018070104-23","doi-asserted-by":"publisher","DOI":"10.1109\/ICT.2016.7500447"},{"key":"IJRSDA.2018070104-24","doi-asserted-by":"publisher","DOI":"10.1007\/s11071-014-1639-z"}],"container-title":["International Journal of Rough Sets and Data Analysis"],"original-title":[],"language":"ng","link":[{"URL":"https:\/\/www.igi-global.com\/viewtitle.aspx?TitleId=206877","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,6]],"date-time":"2022-05-06T12:40:27Z","timestamp":1651840827000},"score":1,"resource":{"primary":{"URL":"https:\/\/services.igi-global.com\/resolvedoi\/resolve.aspx?doi=10.4018\/IJRSDA.2018070104"}},"subtitle":[""],"short-title":[],"issued":{"date-parts":[[2018,7,1]]},"references-count":25,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2018,7]]}},"URL":"https:\/\/doi.org\/10.4018\/ijrsda.2018070104","relation":{},"ISSN":["2334-4598","2334-4601"],"issn-type":[{"value":"2334-4598","type":"print"},{"value":"2334-4601","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,7,1]]}}}