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The implementation of a FFT on the two platforms shows a considerable speed-up in comparison with a single-processor reference architecture. The speed-up is higher in the reconfigurable solution but the MP-SoC provides an easier programming interface that is completely based on C language. The authors\u2019 approach proves that implementing a programmable architecture on FPGA and then programming it using a high-level software language is a viable alternative to designing a dedicated hardware block with a hardware description language (HDL) and mapping it on FPGA.<\/p>","DOI":"10.4018\/jertcs.2010070102","type":"journal-article","created":{"date-parts":[[2010,9,7]],"date-time":"2010-09-07T18:58:24Z","timestamp":1283885904000},"page":"24-43","source":"Crossref","is-referenced-by-count":0,"title":["Implementation of FFT on General-Purpose Architectures for FPGA"],"prefix":"10.4018","volume":"1","author":[{"given":"Fabio","family":"Garzia","sequence":"first","affiliation":[{"name":"Tampere University of Technology, Finland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Roberto","family":"Airoldi","sequence":"additional","affiliation":[{"name":"Tampere University of Technology, Finland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jari","family":"Nurmi","sequence":"additional","affiliation":[{"name":"Tampere University of Technology, Finland"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"2432","reference":[{"key":"jertcs.2010070102-0","doi-asserted-by":"crossref","unstructured":"Ahonen, T., & Nurmi, J. (2006). Programmable switch for shared bus replacement. In Proceedings of the 2006 International Conference on Ph.D. Research in Microelectronics and Electronics (PRIME \u201906) (pp. 241-244). Washington, DC: IEEE. ISBN: 1-4244-0156-9 DOI: 10.1109\/RME.2006.1689941","DOI":"10.1109\/RME.2006.1689941"},{"key":"jertcs.2010070102-1","doi-asserted-by":"crossref","unstructured":"Airoldi, R., Garzia, F., Ahonen, T., Milojevic, D., & Nurmi, J. (2009a). Implementation of W-CDMA cell search on a FPGA based Multi-Processor System-on-Chip with power management. In Proceedings of the IX International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS IX) (LNCS, pp. 88-97). Berlin: Springer Verlag.","DOI":"10.1007\/978-3-642-03138-0_10"},{"key":"jertcs.2010070102-2","doi-asserted-by":"crossref","unstructured":"Airoldi, R., Garzia, F., & Nurmi, J. (2009b). Implementation of a 64-point FFT on a Multi-Processor System-on-Chip. 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