{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,10]],"date-time":"2026-06-10T16:37:59Z","timestamp":1781109479394,"version":"3.54.1"},"reference-count":36,"publisher":"IGI Global Scientific Publishing","issue":"4","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,10,1]]},"abstract":"<p>Source synchronous links for use in multi-synchronous networks-on-chip (NoCs) are becoming the most vulnerable points for correct network operation and must be safeguarded against intra-link delay variations and signal misalignments. The intricacy of matching link net attributes during placement and routing and the growing role of process parameter variations in nanoscale silicon technologies are the root causes for this. This article addresses the challenge of designing a process variation and layout mismatch tolerant link for synchronizer-based GALS NoCs by implementing a self-calibration mechanism. A variation detector senses the variability-induced misalignment between data lines with themselves and with the transmitter clock routed with data in source synchronous links. A suitable delayed replica of the transmitter clock is then selected for safe sampling of misaligned data. The manuscript proves robustness of the link in isolation with respect to a detector-less link, but also assesses integration issues with the downstream synchronizer and switch architecture, proving the benefits in a realistic experimental setting for cost-effective NoCs.<\/p>","DOI":"10.4018\/jertcs.2011100101","type":"journal-article","created":{"date-parts":[[2011,10,19]],"date-time":"2011-10-19T12:19:01Z","timestamp":1319026741000},"page":"1-20","source":"Crossref","is-referenced-by-count":0,"title":["Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design"],"prefix":"10.4018","volume":"2","author":[{"given":"Alessandro","family":"Strano","sequence":"first","affiliation":[{"name":"University of Ferrara, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Carles","family":"Hern\u00e1ndez","sequence":"additional","affiliation":[{"name":"Universidad Polit\u00e9cnica de Valencia, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Federico","family":"Silla","sequence":"additional","affiliation":[{"name":"Universidad Polit\u00e9cnica de Valencia, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Davide","family":"Bertozzi","sequence":"additional","affiliation":[{"name":"University of Ferrara, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"2432","reference":[{"key":"jertcs.2011100101-0","doi-asserted-by":"publisher","DOI":"10.1109\/16.974757"},{"key":"jertcs.2011100101-1","doi-asserted-by":"crossref","unstructured":"Beer, S., Ginosar, R., Priel, M., Dobkin, R., & Kolodny, A. (2010). The devolution of synchronizers. In Proceedings of the IEEE Symposium on Asynchronous Circuits and Systems (pp. 94-103).","DOI":"10.1109\/ASYNC.2010.22"},{"key":"jertcs.2011100101-2","unstructured":"Bonesi, S., Bertozzi, D., Benini, L., & Macii, E. (2008). Process variation tolerant pipeline design through a placement-aware multiple voltage island design style. Design, Automation and Test in Europe, 967-972."},{"key":"jertcs.2011100101-3","doi-asserted-by":"crossref","unstructured":"Borkar, S., Karnik, T., & Vivek, D. (2004). Design and reliability challenges in nanometer technologies. In Proceedings of the 41st Design Automation Conference (p. 75).","DOI":"10.1145\/996566.996588"},{"key":"jertcs.2011100101-4","doi-asserted-by":"publisher","DOI":"10.1109\/4.982424"},{"key":"jertcs.2011100101-5","unstructured":"Collins, H. A., & Nikel, R. E. (1999). DDR-SDRAM, high-speed, source synchronous interfaces create design challenges. Retrieved from http:\/\/www.edn.com\/article\/506435-DDR_SDRAM_high_speed_source_synchronous_interfaces_create_design_challenges.php"},{"key":"jertcs.2011100101-6","doi-asserted-by":"crossref","DOI":"10.1017\/CBO9781139166980","author":"W. J.Dally","year":"1998","journal-title":"Digital systems engineering"},{"key":"jertcs.2011100101-7","unstructured":"Diamos, G., Yalamanchili, S., & Duato, J. (2007). STARS: A system for tuning and actively reconfiguring SoCs link. Paper presented at the DAC Workshop on Diagnostic Services in NoCs."},{"key":"jertcs.2011100101-8","doi-asserted-by":"crossref","unstructured":"Elrabaa, M. E. S. (2006). An all-digital clock frequency capturing circuitry for NRZ data communications. In Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (pp. 106-109).","DOI":"10.1109\/ICECS.2006.379712"},{"key":"jertcs.2011100101-9","doi-asserted-by":"crossref","unstructured":"Ernst, D., Kim, N. S., Das, S., Pant, S., Rao, R., Pham, T., et al. (2003). Razor: A low-power pipeline based on circuit-level timing speculation. In Proceedings of the 36th Annual IEEE\/ACM International Symposium on Microarchitecture (pp. 7-18).","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"jertcs.2011100101-10","doi-asserted-by":"crossref","unstructured":"Faiz-ul-Hassan. Cheng, B., Vanderbauwhede, W., & Rodriguez, F. (2009). Impact of device variability in the communication structures for future synchronous SoC designs. In Proceedings of the International Symposium on System-on-Chip (pp. 68-72).","DOI":"10.1109\/SOCC.2009.5335676"},{"key":"jertcs.2011100101-11","doi-asserted-by":"crossref","unstructured":"Gilabert, F., Ludovici, D., Medardoni, S., Bertozzi, D., Benini, L., & Gaydadjiev, G. N. (2009). Designing regular network-on-chip topologies under technology, architecture and software constraints. In Proceedings of the International Conference on Complex, Intelligent and Software Intensive Systems (pp. 681-687).","DOI":"10.1109\/CISIS.2009.30"},{"key":"jertcs.2011100101-12","doi-asserted-by":"crossref","unstructured":"Hern\u00e1ndez, C., Roca, A., Silla, F., Flich, J., & Duato, J. (2010). Improving the performance of GALS-based NoCs in the presence of process variation. In Proceedings of the Fourth ACM\/IEEE International Symposium on Networks-on-Chip (pp. 35-42).","DOI":"10.1109\/NOCS.2010.13"},{"key":"jertcs.2011100101-13","doi-asserted-by":"crossref","unstructured":"H\u00f6ppner, S., Walter, D., Eisenreich, H., & Sch\u00fcffny, R. (2010). Efficient compensation of delay variations in high-speed network-on-chip data links. In Proceedings of the International Symposium on System on Chip (pp. 55-58).","DOI":"10.1109\/ISSOC.2010.5625534"},{"key":"jertcs.2011100101-14","unstructured":"ITRS. (2007). International technology roadmap for semiconductors. Retrieved from http:\/\/www.itrs.net\/Links\/2007ITRS\/Home2007.htm"},{"key":"jertcs.2011100101-15","doi-asserted-by":"crossref","unstructured":"Jose, A. P., Patounakis, G., & Shepard, K. L. (2005). Near speed-of-light on-chip interconnects using pulsed current-mode signalling. In Proceedings of the Digest of Technical Papers Symposium on VLSI Circuits (pp. 108-111).","DOI":"10.1109\/VLSIC.2005.1469345"},{"key":"jertcs.2011100101-16","doi-asserted-by":"crossref","unstructured":"Kakoee, M. R., Loi, I., & Benini, L. (2010). A new physical routing approach for robust bundled signaling on NoC links. In Proceedings of the 20th Symposium on the Great Lakes (pp. 3-8).","DOI":"10.1145\/1785481.1785485"},{"key":"jertcs.2011100101-17","unstructured":"Kenyon, C., Kornfeld, A., Kuhn, K., Liu, M., Maheshwari, A., Shih, W. et al. (2008). Managing process variation in Intel's 45nm CMOS technology. Intel Technology Journal, 12(2)."},{"key":"jertcs.2011100101-18","author":"M.Kihara","year":"2003","journal-title":"Digital clocks for synchronization and communications"},{"key":"jertcs.2011100101-19","doi-asserted-by":"crossref","unstructured":"Loi, I., Angiolini, F., & Benini, L. (2008). Developing mesochronous synchronizers to enable 3D NoCs. Design, Automation and Test in Europe, 1414-1419.","DOI":"10.1109\/DATE.2008.4484872"},{"key":"jertcs.2011100101-20","doi-asserted-by":"crossref","unstructured":"Ludovici, D., Strano, A., Bertozzi, D., Benini, L., & Gaydadjiev, G. N. (2009). Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture. In Proceedings of the 3rd ACM\/IEEE International Symposium on Networks-on-Chip (pp. 244-249).","DOI":"10.1109\/NOCS.2009.5071473"},{"key":"jertcs.2011100101-21","doi-asserted-by":"crossref","unstructured":"Ludovici, D., Strano, A., Gaydadjiev, G. N., Benini, L., & Bertozzi, D. (2010). Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs. Design, Automation & Test in Europe, 679-684.","DOI":"10.1109\/DATE.2010.5457116"},{"key":"jertcs.2011100101-22","unstructured":"Merdadoni, S., Lajolo, M., & Bertozzi, D. (2008). Variation tolerant NoC design by means of self-calibrating links. Design, Automation and Test in Europe, 1402-1407."},{"key":"jertcs.2011100101-23","doi-asserted-by":"crossref","unstructured":"Mondal, M., Ragheb, T., Wu, X., Aziz, A., & Massoud, Y. (2007). Provisioning on-chip networks under buffered RC interconnect delay variations. In Proceedings of the 8th International Symposium on Quality Electronic Design (pp. 873-878).","DOI":"10.1109\/ISQED.2007.129"},{"key":"jertcs.2011100101-24","doi-asserted-by":"crossref","unstructured":"Moore, S. W., & Taylor, G. S. (2000). Self calibrating clocks for globally asynchronous locally synchronous systems. In Proceedings of the IEEE International Conference on Computer Design (pp. 73-78).","DOI":"10.1109\/ICCD.2000.878271"},{"key":"jertcs.2011100101-25","doi-asserted-by":"crossref","unstructured":"Murali, S., Tamhankar, R., Angiolini, F., Pulling, A., Atienza, D., Benini, L., & De Micheli, G. (2006). Comparison of a timing-error tolerant scheme with a traditional re-transmission mechanism for networks on chips. In Proceedings of the International Symposium on System-on-Chip (pp. 1-4).","DOI":"10.1109\/ISSOC.2006.321983"},{"key":"jertcs.2011100101-26","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2008.59"},{"key":"jertcs.2011100101-27","doi-asserted-by":"crossref","unstructured":"Orshansky, M., & Keutzer, K. (2002). A general probabilistic framework for worst case timing analysis. In Proceedings of the 39th Design Automation Conference (pp. 556- 561).","DOI":"10.1145\/513918.514059"},{"key":"jertcs.2011100101-28","doi-asserted-by":"crossref","unstructured":"Paci, G., Bertozzi, D., & Benini, L. (2009). Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels. Design, Automation & Test in Europe, 1404-1409.","DOI":"10.1109\/DATE.2009.5090884"},{"key":"jertcs.2011100101-29","unstructured":"Panades, I. M., Clermidy, F., Vivet, P., & Greiner, A. (2008). Physical implementation of the DSPIN network-on-chip in the FAUST Architecture. In Proceedings of the International Symposium on Networks-on-Chip (pp. 139-148)."},{"key":"jertcs.2011100101-30","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2007.913186"},{"key":"jertcs.2011100101-31","doi-asserted-by":"crossref","unstructured":"Stergiou, S., Angiolini, F., Carta, S., Raffo, L., Bertozzi, D., & De Micheli, G. (2005). Xpipes Lite: A synthesis oriented design library for networks on chips. In Proceedings of the Conference on Design, Automation and Test in Europe (Vol. 2, pp. 1188-1193).","DOI":"10.1109\/DATE.2005.1"},{"key":"jertcs.2011100101-32","unstructured":"Synopsys. (2007). PrimeTime VX application note - Implementation methodology with variation-aware timing analysis, version 1.0. Mountain View, CA: Synopsys."},{"key":"jertcs.2011100101-33","doi-asserted-by":"crossref","unstructured":"Tran, A. T., Truong, D. N., & Baas, M. B. (2009). A low-cost high-speed source-synchronous interconnection technique for GALS chip multiprocessors. In Proceedings of the IEEE International Symposium on Circuits and Systems (pp. 996-999).","DOI":"10.1109\/ISCAS.2009.5117926"},{"key":"jertcs.2011100101-34","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.834241"},{"key":"jertcs.2011100101-35","doi-asserted-by":"crossref","unstructured":"Yu, Z., & Baas, B. M. (2006). Implementing tile-based chip multiprocessors with GALS clocking style. In Proceedings of the IEEE International Symposium on Circuits and Systems (pp. 174-179).","DOI":"10.1109\/ICCD.2006.4380812"}],"container-title":["International Journal of Embedded and Real-Time Communication Systems"],"original-title":[],"language":"ng","link":[{"URL":"https:\/\/www.igi-global.com\/viewtitle.aspx?TitleId=60151","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T12:28:00Z","timestamp":1654086480000},"score":1,"resource":{"primary":{"URL":"https:\/\/services.igi-global.com\/resolvedoi\/resolve.aspx?doi=10.4018\/jertcs.2011100101"}},"subtitle":[""],"short-title":[],"issued":{"date-parts":[[2011,10,1]]},"references-count":36,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2011,10]]}},"URL":"https:\/\/doi.org\/10.4018\/jertcs.2011100101","relation":{},"ISSN":["1947-3176","1947-3184"],"issn-type":[{"value":"1947-3176","type":"print"},{"value":"1947-3184","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,10,1]]}}}