{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T21:12:38Z","timestamp":1654117958156},"reference-count":16,"publisher":"IGI Global","issue":"4","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,10,1]]},"abstract":"<p>In this paper the authors present the concept and evaluation results of a complex GALS ASIC demonstrator in 40 nm CMOS process. This chip, named Moonrake, compares synchronous and GALS synchronization technology in a homogeneous experimental setting: same baseline designs, same manufacturing process, same die. The chip validates GALS technology for both point-to-point and network-centric on-chip communications, demonstrating its potentials for different applications. The design analysis, measurement and test results confirm the potential of GALS approach for the scaled technologies, showing the significant benefits in respect to area, power, and EMI when it comes to the complex system implementation. Furthermore, 91% of the tests performed on the GALS network-on-chip test structures completed successfully, validating the timing robustness of new area and latency-efficient synchronization schemes and proving that the design flow for GALS synchronization technology can be implemented by means of mainstream industrial tools.<\/p>","DOI":"10.4018\/jertcs.2012100101","type":"journal-article","created":{"date-parts":[[2013,1,14]],"date-time":"2013-01-14T19:22:51Z","timestamp":1358191371000},"page":"1-18","source":"Crossref","is-referenced-by-count":2,"title":["Evaluation of GALS Methods in Scaled CMOS Technology"],"prefix":"10.4018","volume":"3","author":[{"given":"Milo\u0161","family":"Krstic","sequence":"first","affiliation":[{"name":"IHP, Frankfurt (Oder), Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xin","family":"Fan","sequence":"additional","affiliation":[{"name":"IHP, Frankfurt (Oder), Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eckhard","family":"Grass","sequence":"additional","affiliation":[{"name":"IHP, Frankfurt (Oder), Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[{"name":"University of Bologna, Bologna, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M. R.","family":"Kakoee","sequence":"additional","affiliation":[{"name":"University of Bologna, Bologna, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christoph","family":"Heer","sequence":"additional","affiliation":[{"name":"Intel Mobile Communications, Neubiberg, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Birgit","family":"Sanders","sequence":"additional","affiliation":[{"name":"Intel Mobile Communications, Neubiberg, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alessandro","family":"Strano","sequence":"additional","affiliation":[{"name":"Intel Mobile Communications, Neubiberg, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Davide","family":"Bertozzi","sequence":"additional","affiliation":[{"name":"Intel Mobile Communications, Neubiberg, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"2432","reference":[{"key":"jertcs.2012100101-0","doi-asserted-by":"crossref","unstructured":"Beer, S., Ginosar, R., Priel, M., Dobkin, R., & Kolodny, A. (2010). The devolution of synchronizers. In Proceedings of the IEEE Symposium on Asynchronous Circuits and Systems (pp. 94-103).","DOI":"10.1109\/ASYNC.2010.22"},{"key":"jertcs.2012100101-1","doi-asserted-by":"crossref","unstructured":"Beigne, E., Clermidy, F., Durupt, J., Lhermet, H., Miermont, S., & Thonnart, Y. \u2026Vivet, P. (2008). An asynchronous power aware and adaptive NoC based circuit. In Proceedings of the IEEE Symposium on Very Large System Integration Circuits (pp. 190-191).","DOI":"10.1109\/VLSIC.2008.4586002"},{"issue":"3","key":"jertcs.2012100101-2","first-page":"315","article-title":"Petrify: A tool for manipulating concurrent specifications and synthesis of asynchronous controllers.","volume":"80","author":"J.Cortadella","year":"1997","journal-title":"IEICE Transactions on Information and Systems"},{"key":"jertcs.2012100101-3","doi-asserted-by":"crossref","unstructured":"Fan, X., Krsti\u0107, M., & Grass, E. (2009). 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Magali: A reconfigurable digital baseband for 4G telecom applications based on an asynchronous NoC. In Proceedings of the ACM\/IEEE International Symposium on Networks-on-Chip."},{"key":"jertcs.2012100101-8","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.1268991"},{"key":"jertcs.2012100101-9","doi-asserted-by":"crossref","unstructured":"Ludovici, D., Strano, A., Gaydadjiev, G. N., Benini, L., & Bertozzi, D. (2010). Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs. In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (pp. 679-684).","DOI":"10.1109\/DATE.2010.5457116"},{"key":"jertcs.2012100101-10","unstructured":"Panades, I. M., Clermidy, F., Vivet, P., & Greiner, A. (2008). Physical implementation of the DSPIN network-on-chip in the Faust architecture. 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