{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,10]],"date-time":"2026-06-10T15:25:44Z","timestamp":1781105144803,"version":"3.54.1"},"reference-count":10,"publisher":"IGI Global Scientific Publishing","issue":"4","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,10,1]]},"abstract":"<p>This paper presents techniques for measurement and compensation of timing variations in clock and data channels of source-synchronous high-speed serial network-on-chip (NoC) links. Timing mismatch measurements are performed by means of asynchronous sub-sampling. This allows the use of low quality sampling clocks to reduce test hardware overhead for integration into complex MPSoCs (Multiprocessor System-on-Chip) with multiple NoC links. The effect of clock jitter on the measurement results is evaluated. Delay mismatch is compensated by tunable delay cells. The proposed technique enables compensation of delay variations to realize high-speed NoC links with sufficient yield. It is demonstrated at NoC links as part of an MPSoC in 65 nm Complementary Metal Oxide Semiconductor technology, where the calibration significantly reduces bit-error-rates of a 72 GBit\/s (8 GBit\/s per lane) link over 4 mm on-chip interconnect.<\/p>","DOI":"10.4018\/jertcs.2012100103","type":"journal-article","created":{"date-parts":[[2013,1,14]],"date-time":"2013-01-14T14:22:51Z","timestamp":1358173371000},"page":"42-56","source":"Crossref","is-referenced-by-count":1,"title":["On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links"],"prefix":"10.4018","volume":"3","author":[{"given":"Sebastian","family":"H\u00f6ppner","sequence":"first","affiliation":[{"name":"Technische Universit\u00e4t Dresden, Dresden, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dennis","family":"Walter","sequence":"additional","affiliation":[{"name":"Technische Universit\u00e4t Dresden, Dresden, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Georg","family":"Ellguth","sequence":"additional","affiliation":[{"name":"Technische Universit\u00e4t Dresden, Dresden, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ren\u00e9","family":"Sch\u00fcffny","sequence":"additional","affiliation":[{"name":"Technische Universit\u00e4t Dresden, Dresden, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"2432","reference":[{"key":"jertcs.2012100103-0","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2083706"},{"key":"jertcs.2012100103-1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910807"},{"key":"jertcs.2012100103-2","first-page":"1","article-title":"A compact clock generator for heterogeneous GALS MPSoCs in 65-nm CMOS technology.","author":"S.H\u00f6ppner","year":"2012","journal-title":"IEEE Transactions on Very Large Scale Integration Systems"},{"key":"jertcs.2012100103-3","doi-asserted-by":"crossref","unstructured":"H\u00f6ppner, S., Walter, D., Eisenreich, H., & Sch\u00fcffny, R. (2010). Efficient compensation of delay variations in high-speed network-on-chip data links. In Proceedings of the International Symposium on System on Chip (pp. 55-58).","DOI":"10.1109\/ISSOC.2010.5625534"},{"key":"jertcs.2012100103-4","doi-asserted-by":"crossref","unstructured":"H\u00f6ppner, S., Walter, D., Ellguth, G., & Sch\u00fcffny, R. (2011). Mismatch characterization of high-speed NoC links using asynchronous sub-sampling. In Proceedings of the International Symposium on System on Chip (pp. 112-115).","DOI":"10.1109\/ISSOC.2011.6089695"},{"key":"jertcs.2012100103-5","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1976.1162830"},{"key":"jertcs.2012100103-6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2036761"},{"key":"jertcs.2012100103-7","doi-asserted-by":"crossref","unstructured":"Schaub, J., Gebara, F., Nguyen, T., Vo, I., Pena, J., & Acharyya, D. (2008). On-chip jitter and oscilloscope circuits using an asynchronous sample clock. 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