{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,10]],"date-time":"2026-06-10T15:11:55Z","timestamp":1781104315236,"version":"3.54.1"},"reference-count":7,"publisher":"IGI Global Scientific Publishing","issue":"4","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,10,1]]},"abstract":"<p>Emerging technologies for nanoscale computation such as self-assembled nanowire arrays present specific challenges for logic synthesis. On the one hand, they provide an unprecedented density of bits with a high degree of parallelism. On the other hand, they are characterized by high defect rates. Also they often exhibit inherent randomness in the interconnects due to the stochastic nature of self-assembly. We describe a general method for synthesizing logic that exploits both the parallelism and the random effects. Our approach is based on stochastic computation with parallel bit streams. Circuits are synthesized through functional decomposition with symbolic data structures called multiplicative binary moment diagrams. Synthesis produces designs with randomized parallel components\u2014and operations and multiplexing\u2014that are readily implemented in nanowire crossbar arrays. Synthesis results for benchmarks circuits show that our technique maps circuit designs onto nanowire arrays effectively.<\/p>","DOI":"10.4018\/jnmc.2009120903","type":"journal-article","created":{"date-parts":[[2010,4,16]],"date-time":"2010-04-16T16:01:26Z","timestamp":1271433686000},"page":"39-57","source":"Crossref","is-referenced-by-count":5,"title":["The Synthesis of Stochastic Circuits for Nanoscale Computation"],"prefix":"10.4018","volume":"1","author":[{"given":"Weikang","family":"Qian","sequence":"first","affiliation":[{"name":"University of Minnesota, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"John","family":"Backes","sequence":"additional","affiliation":[{"name":"University of Minnesota, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Marc D.","family":"Riedel","sequence":"additional","affiliation":[{"name":"University of Minnesota, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"2432","reference":[{"key":"jnmc.2009120903-0","unstructured":"Asgar, Z., Kodakara, S., & Lilja, D. (2005). Fault-tolerant image processing using stochastic logic (Tech. Rep.). Retrieved from http:\/\/www.zasgar.net\/zain\/publications\/publications.php"},{"key":"jnmc.2009120903-1","doi-asserted-by":"crossref","unstructured":"Bryant, R., & Chen, Y. (1995). Verification of arithmetic circuits with binary moment diagrams. In Proceedings of the 32nd Design Automation Conference (DAC \u201995), San Francisco (pp.535-541).","DOI":"10.1145\/217474.217583"},{"key":"jnmc.2009120903-2","doi-asserted-by":"publisher","DOI":"10.1145\/1084748.1084750"},{"key":"jnmc.2009120903-3","unstructured":"FENA. (2006). Mission statement. Retrieved from http:\/\/www.fena.org"},{"key":"jnmc.2009120903-4","unstructured":"International Technology Roadmap for Semiconductors. (2006). ITRS 2006 update. Retrieved from http:\/\/www.itrs.net\/Links\/2006Update\/2006UpdateFinal.htm"},{"key":"jnmc.2009120903-5","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1088\/0957-4484\/18\/3\/035204","article-title":"Nano\/CMOS architectures using a field-programmable nanowire interconnect.","volume":"18","author":"G.Snider","year":"2007","journal-title":"Nanotechnology"},{"key":"jnmc.2009120903-6","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/16\/6\/045"}],"container-title":["International Journal of Nanotechnology and Molecular Computation"],"original-title":[],"language":"ng","link":[{"URL":"https:\/\/www.igi-global.com\/viewtitle.aspx?TitleId=40364","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T17:00:48Z","timestamp":1654102848000},"score":1,"resource":{"primary":{"URL":"https:\/\/services.igi-global.com\/resolvedoi\/resolve.aspx?doi=10.4018\/jnmc.2009120903"}},"subtitle":[""],"short-title":[],"issued":{"date-parts":[[2009,10,1]]},"references-count":7,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2009,10]]}},"URL":"https:\/\/doi.org\/10.4018\/jnmc.2009120903","relation":{},"ISSN":["1941-6318","1941-6326"],"issn-type":[{"value":"1941-6318","type":"print"},{"value":"1941-6326","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,10,1]]}}}