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In the world of multi-core processors, the STI Cell Broadband Engine (BE) stands out as a heterogeneous 9-core processor with a PowerPC host processor (PPE) and 8 synergic processor engines (SPEs). The Cell BE architecture is designed to improve upon conventional processors in graphics and related areas by integrating 8 computation engines each with multiple execution units and large register sets to achieve a high performance per area return. In this paper, we discuss the parallelization, implementation and performance evaluation of an edge detection image processing application based on the Roberts edge detector on the Cell BE. The authors report the edge detection performance measured on a computer with one Cell processor and with varying numbers of synergic processor engines enabled. These results are compared to the results obtained on the Cell\u2019s single PPE with all 8 SPEs disabled. The results indicate that edge detection performs 10 times faster on the Cell BE than on modern RISC processors.<\/p>","DOI":"10.4018\/jitr.2009062906","type":"journal-article","created":{"date-parts":[[2010,4,30]],"date-time":"2010-04-30T13:09:23Z","timestamp":1272632963000},"page":"81-91","source":"Crossref","is-referenced-by-count":1,"title":["Parallelization and Performance Evaluation of an Edge Detection Algorithm on a Streaming Multi-Core Engine"],"prefix":"10.4018","volume":"2","author":[{"given":"Hashir Karim","family":"Kidwai","sequence":"first","affiliation":[{"name":"UAE University, UAE"}]},{"given":"Fadi N.","family":"Sibai","sequence":"additional","affiliation":[{"name":"UAE University, UAE"}]},{"given":"Tamer","family":"Rabie","sequence":"additional","affiliation":[{"name":"UAE University, UAE"}]}],"member":"2432","reference":[{"key":"jitr.2009062906-0","doi-asserted-by":"publisher","DOI":"10.1109\/TPAMI.1986.4767851"},{"key":"jitr.2009062906-1","unstructured":"Castleman, K. R. (1979). Digital Image Processing, Prentice-Hall."},{"key":"jitr.2009062906-2","unstructured":"Cico, L., Cooper, R., & Greene, J. (2006). Performance and Programmability of the IBM\/Sony\/Toshiba Cell Broadband Engine Processor. Paper presented at the Workshop on Edge Computing Using New Commodity Architectures (EDGE), May 23-24, 2006, Univ. of North Carolina, Chapel Hill"},{"key":"jitr.2009062906-3","unstructured":"Corp, I. B. M. (a) Cell Broadband EngineTM Programming Handbook. http:\/\/www-01.ibm.com\/chips\/techlib\/techlib.nsf\/ techdocs\/9F820A5FFA3ECE8C8725716A0062585F"},{"key":"jitr.2009062906-4","unstructured":"Corp, I. B. M. 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