{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,29]],"date-time":"2022-03-29T18:31:46Z","timestamp":1648578706272},"reference-count":20,"publisher":"International Academy Publishing (IAP)","issue":"3","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["JCP"],"DOI":"10.4304\/jcp.8.3.594-604","type":"journal-article","created":{"date-parts":[[2013,2,28]],"date-time":"2013-02-28T03:45:34Z","timestamp":1362023134000},"source":"Crossref","is-referenced-by-count":1,"title":["An Efficient Implementation of H.264\/AVC Integer Motion Estimation Algorithm on Coarse-grained Reconfigurable Computing System"],"prefix":"10.17706","volume":"8","author":[{"given":"Kiem-Hung","family":"Nguyen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peng","family":"Cao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xue-Xiang","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"7163","published-online":{"date-parts":[[2013,3,1]]},"reference":[{"key":"ref1","volume-title":"Richardson The H 264 advanced video compression standard","author":"Iain","year":"2010","unstructured":"[1] Iain E. Richardson: The H.264 advanced video compression standard, second edition, 2010, John Wiley & Sons, Ltd."},{"key":"ref2","article-title":"Tu-Chih Wang; Bing-Yu Hsieh; Liang-Gee Chen: Hardware architecture design for variable block size motion estimation in MPEG-4 AVC\/JVT\/ITU-T H.264","volume-title":"Proceedings of the International Symposium on Circuits and Systems","year":"2003","unstructured":"[2] Yu-Wen Huang; Tu-Chih Wang; Bing-Yu Hsieh; Liang-Gee Chen: Hardware architecture design for variable block size motion estimation in MPEG-4 AVC\/JVT\/ITU-T H.264, Proceedings of the International Symposium on Circuits and Systems, 2003. IEEE."},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2005.1561858"},{"key":"ref4","volume-title":"Ali Akoglu A Coarse grained and hybrid reconfigurable architecture with flexible NOC router for variable block size motion estimation","author":"Verma","year":"2008","unstructured":"[5] Ruchika Verma, Ali Akoglu: A Coarse grained and hybrid reconfigurable architecture with flexible NOC router for variable block size motion estimation, 2008, IEEE."},{"issue":"Iss. 5","key":"ref5","first-page":"349","article-title":"J.V. MCCANNY, S. Sezer.: \"Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding","volume":"4","year":"2010","unstructured":"[6] L. LU, J.V. MCCANNY, S. Sezer.: \"Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding\", IET Comput. Digit. Tech., 2010, Vol. 4, Iss. 5, pp. 349\u2013364.","journal-title":"IET Comput Digit Tech"},{"key":"ref6","volume-title":"Darren C Cronquist Paul Franklin Jason Secosky and Stefan G Berg \"Mapping Applications to the RaPiD Configurable Architecture FPGAs for Custom Computing Machines","author":"Ebeling","year":"1997","unstructured":"[7] Carl Ebeling, Darren C. Cronquist, Paul Franklin, Jason Secosky, and Stefan G. Berg: \"Mapping Applications to the RaPiD Configurable Architecture, FPGAs for Custom Computing Machines\", 1997, IEEE."},{"key":"ref7","article-title":"Leiba Liu, Shaajun Wei: \"Automatic Contexts Switch in Loop Pipeline for Embedded Coarse-grained Reconfigurable Processor","volume-title":"International Conference on Communications Circuits and Systems","author":"Sudang","year":"2008","unstructured":"[8] Sudang Yu, Leiba Liu, Shaajun Wei: \"Automatic Contexts Switch in Loop Pipeline for Embedded Coarse-grained Reconfigurable Processor\", International Conference on Communications, Circuits and Systems, 2008, IEEE."},{"key":"ref8","volume-title":"Michael Scheppler Will Moffat Bingfeng Mei Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes","year":"2005","unstructured":"[9] Francisco-Javier Veredas, Michael Scheppler, Will Moffat, Bingfeng Mei: Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes, IEEE, 2005."},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1587\/transinf.E93.D.3202"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-3636-9"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/83.350809"},{"key":"ref13","article-title":"Fast integer pel and fractional pel motion estimation for JVT, JVT-F017","volume-title":"6th JVT Meeting Awaji","author":"Chen","year":"2002","unstructured":"[18] Chen, Z., Zhou, P., & He, Y.: Fast integer pel and fractional pel motion estimation for JVT, JVT-F017, 6th JVT Meeting, Awaji, December, 2002."},{"key":"ref13","doi-asserted-by":"crossref","unstructured":"[3] S.Y. Yap, J.V. McCanny, A VLSI architecture for variable block size video motion estimation, IEEE transactions on circuits and systems-II: express briefs, VOL.51, No.7, July 2004.","DOI":"10.1109\/TCSII.2004.829555"},{"key":"ref13","doi-asserted-by":"crossref","unstructured":"[11] X. Technologies, \"XPP-III Processor Overview\", White Paper, July 13 2006.","DOI":"10.7748\/en.13.9.3.s8"},{"key":"ref13","doi-asserted-by":"crossref","unstructured":"[12] B. Mei, S. Vernalde, D. Verkest, et al., \"ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix,\" 2003, pp. 61-70.","DOI":"10.1007\/978-3-540-45234-8_7"},{"key":"ref13","doi-asserted-by":"crossref","unstructured":"[15] Kiran Bondalapati, Viktor K. Prasanna: Mapping loops onto reconfigurable architectures, International workshop on field programmable logic, September, 1998.","DOI":"10.1007\/BFb0055254"},{"key":"ref13","unstructured":"[16] JM reference software, http:\/\/iphome.hhi.de\/suering\/tml\/."},{"key":"ref13","unstructured":"[19] http:\/\/suif.stanford.edu\/."},{"key":"ref13","doi-asserted-by":"crossref","unstructured":"[20] H. T. Kung and P. L. Lehman: \"Systolic (VLSI) Arrays for Relational Database Operations\", Proc. ACM-Sigmod 1980 Int'l Conf. Management of Data, p.105, 1980.","DOI":"10.1145\/582250.582267"}],"container-title":["Journal of Computers"],"original-title":[],"deposited":{"date-parts":[[2019,7,10]],"date-time":"2019-07-10T05:35:18Z","timestamp":1562736918000},"score":1,"resource":{"primary":{"URL":"http:\/\/ojs.academypublisher.com\/index.php\/jcp\/article\/view\/9217"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,3,1]]},"references-count":20,"journal-issue":{"issue":"3","published-online":{"date-parts":[[2013,3,1]]}},"URL":"https:\/\/doi.org\/10.4304\/jcp.8.3.594-604","relation":{},"ISSN":["1796-203X"],"issn-type":[{"value":"1796-203X","type":"print"}],"subject":[],"published":{"date-parts":[[2013,3,1]]}}}