{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,2]],"date-time":"2026-04-02T15:47:20Z","timestamp":1775144840345,"version":"3.50.1"},"reference-count":0,"publisher":"Universitatsbibliothek der Ruhr-Universitat Bochum","issue":"1","license":[{"start":{"date-parts":[[2024,12,9]],"date-time":"2024-12-09T00:00:00Z","timestamp":1733702400000},"content-version":"unspecified","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["TCHES"],"abstract":"<jats:p>Falcon is a lattice-based quantum-resistant digital signature scheme renowned for its high signature generation\/verification speed and compact signature size. The scheme has been selected to be drafted in the third round of the post-quantum cryptography (PQC) standardization process due to its unique attributes and robust security features. Despite its strengths, there has been a lack of research on hardware acceleration, primarily due to its complex calculation flow and floating-point operations, which hinders its widespread adoption. To address this issue, we propose FalconSign, a high-performance, configurable crypto-processor designed to accelerate Falcon signature generation on FPGA\/ASIC through algorithmhardware co-design. Our approach involves a new scheduling flow and architecture for Fast-Fourier Sampling to enhance computing unit reuse and reduce processing time. Additionally, we introduce several optimized modules, including configurable randomness generation units, parallel floating-point processing units, and an optimized SamplerZ module, to improve execution efficiency. Furthermore, this paper presents a finely optimized hardware accelerator for the Falcon scheme. Our FPGA implementation results demonstrate a throughput improvement of approximately 5.1 x compared to state-of-the-art designs, with 2.8x\/4.5x\/4.2x\/3.2x fewer in the area (LUTs\/FFs\/DSPs\/BRAMs)-time product, for NIST security level V. The crypto-processor occupies an area of 0.71 mm2 and achieves 5.2k OPS at throughput on the TSMC 28nm process for NIST security level I.<\/jats:p>","DOI":"10.46586\/tches.v2025.i1.203-226","type":"journal-article","created":{"date-parts":[[2024,12,10]],"date-time":"2024-12-10T13:56:09Z","timestamp":1733838969000},"page":"203-226","source":"Crossref","is-referenced-by-count":12,"title":["FalconSign: An Efficient and High-Throughput Hardware Architecture for Falcon Signature Generation"],"prefix":"10.46586","volume":"2025","author":[{"given":"Yi","family":"Ouyang","sequence":"first","affiliation":[]},{"given":"Yihong","family":"Zhu","sequence":"additional","affiliation":[]},{"given":"Wenping","family":"Zhu","sequence":"additional","affiliation":[]},{"given":"Bohan","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Zirui","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Hanning","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Qichao","family":"Tao","sequence":"additional","affiliation":[]},{"given":"Min","family":"Zhu","sequence":"additional","affiliation":[]},{"given":"Shaojun","family":"Wei","sequence":"additional","affiliation":[]},{"given":"Leibo","family":"Liu","sequence":"additional","affiliation":[]}],"member":"25480","published-online":{"date-parts":[[2024,12,9]]},"container-title":["IACR Transactions on Cryptographic Hardware and Embedded Systems"],"original-title":[],"link":[{"URL":"https:\/\/tches.iacr.org\/index.php\/TCHES\/article\/download\/11927\/11786","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/tches.iacr.org\/index.php\/TCHES\/article\/download\/11927\/11786","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,10]],"date-time":"2024-12-10T13:56:10Z","timestamp":1733838970000},"score":1,"resource":{"primary":{"URL":"https:\/\/tches.iacr.org\/index.php\/TCHES\/article\/view\/11927"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12,9]]},"references-count":0,"journal-issue":{"issue":"1","published-online":{"date-parts":[[2024,12,9]]}},"URL":"https:\/\/doi.org\/10.46586\/tches.v2025.i1.203-226","relation":{},"ISSN":["2569-2925"],"issn-type":[{"value":"2569-2925","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,12,9]]}}}