{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,1]],"date-time":"2026-08-01T16:44:07Z","timestamp":1785602647032,"version":"3.56.0"},"reference-count":0,"publisher":"Universitatsbibliothek der Ruhr-Universitat Bochum","issue":"3","license":[{"start":{"date-parts":[[2025,6,5]],"date-time":"2025-06-05T00:00:00Z","timestamp":1749081600000},"content-version":"unspecified","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["TCHES"],"abstract":"<jats:p>This work showcases Quatorze-bis, a state-of-the-art Number Theoretic Transform circuit for TFHE-like cryptosystems on FPGAs. It contains a novel modular multiplication design for modular multiplication with a constant for a constant modulus. This modular multiplication design does not require any DSP units or any dedicated multiplier unit, nor does it require extra logic when compared to the state-of-the-art modular multipliers. Furthermore, we present an implementation of a constant multiplier Number Theoretic Transform design for TFHE-like schemes. Lastly, we use this Number Theoretic Transform design to implement a FINAL hardware accelerator for the AMD Alveo U55c which improves the Throughput metric of TFHE-like cryptosystems on FPGAs by a factor 9.28x over Li et al.\u2019s NFP CHES 2024 accelerator and by 10-25% over the absolute state-of-the-art design FPT [vBDTV23] while using one third of FPTs DSPs.<\/jats:p>","DOI":"10.46586\/tches.v2025.i3.293-316","type":"journal-article","created":{"date-parts":[[2025,6,9]],"date-time":"2025-06-09T09:37:36Z","timestamp":1749461856000},"page":"293-316","source":"Crossref","is-referenced-by-count":2,"title":["FINAL bootstrap acceleration on FPGA using DSP-free constant-multiplier NTTs"],"prefix":"10.46586","volume":"2025","author":[{"given":"Jonas","family":"Bertels","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hilder V. L.","family":"Pereira","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ingrid","family":"Verbauwhede","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"25480","published-online":{"date-parts":[[2025,6,5]]},"container-title":["IACR Transactions on Cryptographic Hardware and Embedded Systems"],"original-title":[],"link":[{"URL":"https:\/\/ojs.ub.rub.de\/index.php\/TCHES\/article\/download\/12218\/12025","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/ojs.ub.rub.de\/index.php\/TCHES\/article\/download\/12218\/12025","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,9]],"date-time":"2025-06-09T09:37:37Z","timestamp":1749461857000},"score":1,"resource":{"primary":{"URL":"https:\/\/ojs.ub.rub.de\/index.php\/TCHES\/article\/view\/12218"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6,5]]},"references-count":0,"journal-issue":{"issue":"3","published-online":{"date-parts":[[2025,6,5]]}},"URL":"https:\/\/doi.org\/10.46586\/tches.v2025.i3.293-316","relation":{},"ISSN":["2569-2925"],"issn-type":[{"value":"2569-2925","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,6,5]]}}}