{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"institution":[{"id":[{"id":"https:\/\/ror.org\/03mb6wj31","id-type":"ROR","asserted-by":"publisher"},{"id":"https:\/\/www.isni.org\/000000041937028X","id-type":"ISNI","asserted-by":"publisher"},{"id":"https:\/\/www.wikidata.org\/entity\/Q1640731","id-type":"wikidata","asserted-by":"publisher"}],"name":"Universitat Polit\u00e8cnica de Catalunya","acronym":["UPC"]}],"indexed":{"date-parts":[[2026,1,29]],"date-time":"2026-01-29T17:36:34Z","timestamp":1769708194630,"version":"3.49.0"},"reference-count":0,"publisher":"Universitat Polit\u00e8cnica de Catalunya","license":[{"content-version":"vor","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"abstract":"<jats:p>The landscape of High Performance Computing (HPC) system architectures keeps expanding with new technologies and increased complexity. To improve the efficiency of next-generation compute devices, architects are looking for solutions beyond the commodity CPU approach. In 2021, the five most powerful supercomputers in the world use either GP-GPU (General-purpose computing on graphics processing units) accelerators or a customized CPU specially designed to target HPC applications. This trend is only expected to grow in the next years motivated by the compute demands of science and industry.\r\nAs architectures evolve, the ecosystem of tools and applications must follow. The choices in the number of cores in a socket, the floating point-units per core and the bandwidth through the memory hierarchy among others, have a large impact in the power consumption and compute capabilities of the devices. To balance CPU and accelerators, designers require accurate tools for analyzing and predicting the impact of new architectural features on the performance of complex scientific applications at scale. In such a large design space, capturing and modeling with simulators the complex interactions between the system software and\r\nhardware components is a defying challenge. Moreover, applications must be able to exploit those designs with aggressive compute capabilities and memory bandwidth configurations. Algorithms and data structures will need to be redesigned accordingly to expose a high degree of data-level parallelism allowing them to scale in large systems. Therefore, next-generation computing devices will be the result of a co-design effort in hardware and applications supported by advanced simulation tools. In this thesis, we focus our work on the co-design of scientific applications and long vector architectures. We significantly extend a multi-scale simulation toolchain enabling accurate performance and power estimations of large-scale HPC systems. Through simulation, we explore the large design space in current HPC trends over a wide range of applications.\r\nWe extract speedup and energy consumption figures analyzing the trade-offs and optimal configurations for each of the applications. We describe in detail the optimization process of two challenging applications on real vector accelerators, achieving outstanding operation performance and full memory bandwidth utilization. Overall, we provide evidence-based\r\narchitectural and programming recommendations that will serve as hardware and software co-design guidelines for the next generation of specialized compute devices.<\/jats:p>\n                <jats:p>El panorama de las arquitecturas de los sistemas para la Computaci\u00f3n de Alto Rendimiento (HPC, de sus siglas en ingl\u00e9s) sigue expandi\u00e9ndose con nuevas tecnolog\u00edas y complejidad adicional. Para mejorar la eficiencia de la pr\u00f3xima generaci\u00f3n de dispositivos de computaci\u00f3n, los arquitectos est\u00e1n buscando soluciones m\u00e1s all\u00e1 de las CPUs. En 2021, los cinco supercomputadores m\u00e1s potentes del mundo utilizan aceleradores gr\u00e1ficos aplicados a prop\u00f3sito general (GP-GPU, de sus siglas en ingl\u00e9s) o CPUs dise\u00f1adas especialmente para aplicaciones HPC. En los pr\u00f3ximos a\u00f1os, se espera que esta tendencia siga creciendo motivada por las demandas de m\u00e1s potencia de computaci\u00f3n de la ciencia y la industria. A medida que las arquitecturas evolucionan, el ecosistema de herramientas y aplicaciones les debe seguir. Las decisiones eligiendo el n\u00famero de n\u00facleos por z\u00f3calo, las unidades de coma flotante por n\u00facleo y el ancho de banda a trav\u00e9s de la jerarqu\u00eda de memor\u00eda entre otros, tienen un gran impacto en el consumo de energ\u00eda y las capacidades de c\u00f3mputo de los dispositivos. Para equilibrar las CPUs y los aceleradores, los dise\u00f1adores deben utilizar herramientas precisas para analizar y predecir el impacto de nuevas caracter\u00edsticas de la arquitectura en el rendimiento de complejas aplicaciones cient\u00edficas a gran escala. Dado semejante espacio de dise\u00f1o, capturar y modelar con simuladores las complejas interacciones entre el software de sistema y los componentes de hardware es un reto desafiante. Adem\u00e1s, las aplicaciones deben ser capaces de explotar tales dise\u00f1os con agresivas capacidades de c\u00f3mputo y ancho de banda de memoria. Los algoritmos y estructuras de datos deber\u00e1n ser redise\u00f1adas para exponer un alto grado de paralelismo de datos permitiendo as\u00ed escalarlos en grandes sistemas. Por lo tanto, la siguiente generaci\u00f3n de disp\u00f3sitivos de c\u00e1lculo ser\u00e1 el resultado de un esfuerzo de codise\u00f1o tanto en hardware como en aplicaciones y soportado por avanzadas herramientas de simulaci\u00f3n. En esta tesis, centramos nuestro trabajo en el codise\u00f1o de aplicaciones cient\u00edficas y arquitecturas vectoriales largas. Extendemos significativamente una serie de herramientas para la simulaci\u00f3n multiescala permitiendo as\u00ed obtener estimaciones de rendimiento y potencia de sistemas HPC de gran escala. A trav\u00e9s de simulaciones, exploramos el gran espacio de dise\u00f1o de las tendencias actuales en HPC sobre un amplio rango de aplicaciones. Extraemos datos sobre la mejora y el consumo energ\u00e9tico analizando las contrapartidas y las configuraciones \u00f3ptimas para cada una de las aplicaciones. Describimos en detalle el proceso de optimizaci\u00f3n de dos aplicaciones en aceleradores vectoriales, obteniendo un rendimiento extraordinario a nivel de operaciones y completa utilizaci\u00f3n del ancho de memoria disponible. Con todo, ofrecemos recomendaciones emp\u00edricas a nivel de arquitectura y programaci\u00f3n que servir\u00e1n como instrucciones para dise\u00f1ar mejor hardware y software para la siguiente generaci\u00f3n de dispositivos de c\u00e1lculo especializados.<\/jats:p>","DOI":"10.5821\/dissertation-2117-368618","type":"dissertation","created":{"date-parts":[[2023,7,19]],"date-time":"2023-07-19T01:44:03Z","timestamp":1689731043000},"approved":{"date-parts":[[2022,5,23]]},"source":"Crossref","is-referenced-by-count":0,"title":["On the co-design of scientific applications and long vector architectures"],"prefix":"10.5821","author":[{"sequence":"additional","affiliation":[]},{"given":"Constantino","family":"G\u00f3mez Crespo","sequence":"first","affiliation":[]}],"member":"3865","container-title":[],"original-title":[],"deposited":{"date-parts":[[2026,1,29]],"date-time":"2026-01-29T06:33:42Z","timestamp":1769668422000},"score":1,"resource":{"primary":{"URL":"https:\/\/hdl.handle.net\/2117\/368618"}},"subtitle":[],"editor":[{"given":"Filippo","family":"Mantovani","sequence":"first","affiliation":[]},{"given":"Marc","family":"Casas","sequence":"additional","affiliation":[]}],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":0,"URL":"https:\/\/doi.org\/10.5821\/dissertation-2117-368618","relation":{},"subject":[]}}