{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"institution":[{"id":[{"id":"https:\/\/ror.org\/03mb6wj31","id-type":"ROR","asserted-by":"publisher"},{"id":"https:\/\/www.isni.org\/000000041937028X","id-type":"ISNI","asserted-by":"publisher"},{"id":"https:\/\/www.wikidata.org\/entity\/Q1640731","id-type":"wikidata","asserted-by":"publisher"}],"name":"Universitat Polit\u00e8cnica de Catalunya","acronym":["UPC"]}],"indexed":{"date-parts":[[2026,1,28]],"date-time":"2026-01-28T18:53:54Z","timestamp":1769626434372,"version":"3.49.0"},"reference-count":0,"publisher":"Universitat Polit\u00e8cnica de Catalunya","license":[{"content-version":"vor","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/es\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"abstract":"<jats:p>SIMD instruction sets are a key feature in current general purpose and high performance architectures. SIMD instructions apply in parallel the same operation to a group of data, commonly known as vector. A single SIMD\/vector instruction can, thus, replace a sequence of scalar instructions. Consequently, the number of instructions can be greatly reduced leading to improved execution times.\r\nHowever, SIMD instructions are not widely exploited by the vast majority of programmers. In many cases, taking advantage of these instructions relies on the compiler. Nevertheless, compilers struggle with the automatic vectorization of codes. Advanced programmers are then compelled to exploit SIMD units by hand, using low-level hardware-specific intrinsics. This approach is cumbersome, error prone and not portable across SIMD architectures.\r\nThis thesis targets OpenMP to tackle the underuse of SIMD instructions from three main areas of the programming model: language constructions, compiler code optimizations and runtime algorithms. We choose the Intel Xeon Phi coprocessor (Knights Corner) and its 512-bit SIMD instruction set for our evaluation process. We make four contributions aimed at improving the exploitation of SIMD instructions in this scope.\r\nOur first contribution describes a compiler vectorization infrastructure suitable for OpenMP. This infrastructure targets for-loops and whole functions. We define a set of attributes for expressions that determine how the code is vectorized. Our vectorization infrastructure also implements support for several advanced vector features. This infrastructure is proven to be effective in the vectorization of complex codes and it is the basis upon which we build the following two contributions.\r\nThe second contribution introduces a proposal to extend OpenMP 3.1 with SIMD parallelism. Essential parts of this work have become key features of the SIMD proposal included in OpenMP 4.0. We define the \"simd\" and \"simd for\" directives that allow programmers to describe SIMD parallelism of loops and whole functions. Furthermore, we propose a set of optional clauses that leads the compiler to generate a more efficient vector code. These SIMD extensions improve the programming efficiency when exploiting SIMD resources. Our evaluation on the Intel Xeon Phi coprocessor shows that our SIMD proposal allows the compiler to efficiently vectorize codes poorly or not vectorized automatically with the Intel C\/C++ compiler. \r\nIn the third contribution, we propose a vector code optimization that enhances overlapped vector loads. These vector loads redundantly read from memory scalar elements already loaded by other vector loads. Our vector code optimization improves the memory usage of these accesses by means of building a vector register cache and exploiting register-to-register instructions. Our proposal also includes a new clause (overlap) in the context of the SIMD extensions for OpenMP of our first contribution. This new clause allows enabling, disabling and tuning this optimization on demand.\r\nThe last contribution tackles the exploitation of SIMD instructions in the OpenMP barrier and reduction primitives. We propose a new combined barrier and reduction tree scheme specifically designed to make the most of SIMD instructions. Our barrier algorithm takes advantage of simultaneous multi-threading technology (SMT) and it utilizes SIMD memory instructions in the synchronization process.\r\nThe four contributions of this thesis are an important step in the direction of a more common and generalized use of SIMD instructions. Our work is having an outstanding impact on the whole OpenMP community, ranging from users of the programming model to compiler and runtime implementations. Our proposals in the context of OpenMP improves the programmability of the programming model, the overhead of runtime services and the execution time of applications by means of a better use of SIMD.<\/jats:p>\n                <jats:p>Los juegos de instrucciones SIMD son un componente clave en las arquitecturas de prop\u00f3sito general y de alto rendimiento actuales. Estas instrucciones aplican en paralelo la misma operaci\u00f3n a un conjunto de datos, conocido como vector. Una instrucci\u00f3n SIMD\/vectorial puede sustituir una secuencia de instrucciones escalares. As\u00ed, el n\u00famero de instrucciones puede ser reducido considerablemente, dando lugar a mejores tiempos de ejecuci\u00f3n.\r\nNo obstante, las instrucciones SIMD no son explotadas ampliamente por la mayor\u00eda de programadores. En general, beneficiarse de estas instrucciones depende del compilador. Sin embargo, los compiladores tienen dificultades con la vectorizaci\u00f3n autom\u00e1tica de c\u00f3digos por lo que los programadores avanzados se ven obligados a explotar las unidades SIMD manualmente, empleando intr\u00ednsecas de bajo nivel espec\u00edficas del hardware. Esta aproximaci\u00f3n es costosa, propensa a errores y no portable entre arquitecturas.\r\nEsta tesis se centra en el modelo de programaci\u00f3n OpenMP para abordar el poco uso de las instrucciones SIMD desde tres \u00e1reas: construcciones del lenguaje, optimizaciones de c\u00f3digo del compilador y algoritmos del runtime. Hemos escogido el coprocesador Intel Xeon Phi (Knights Corner) y su juego de instrucciones SIMD de 512 bits para nuestra evaluaci\u00f3n. Realizamos cuatro contribuciones para mejorar la explotaci\u00f3n de las instrucciones SIMD en este \u00e1mbito.\r\nNuestra primera contribuci\u00f3n describe una infraestructura de vectorizaci\u00f3n de compilador adecuada para OpenMP. Esta infraestructura tiene como objetivo la vectorizaci\u00f3n de bucles y funciones. Para ello definimos un conjunto de atributos que determina como se vectoriza el c\u00f3digo. Nuestra evaluaci\u00f3n demuestra la efectividad de esta infraestructura en la vectorizaci\u00f3n de c\u00f3digos complejos. Esta infraestructura es la base de las dos propuestas siguientes.\r\nEn la segunda contribuci\u00f3n proponemos una extensi\u00f3n SIMD para de OpenMP 3.1. Partes esenciales de este trabajo se han convertido en caracter\u00edsticas clave de la propuesta sobre SIMD incluida en OpenMP 4.0. Definimos las directivas \u2018simd\u2019 y \u2018simd for\u2019 que permiten a los programadores describir paralelismo SIMD de bucles y funciones. Adem\u00e1s, proponemos un conjunto de cl\u00e1usulas opcionales que permiten que el compilador genere c\u00f3digo vectorial m\u00e1s eficiente. Nuestra evaluaci\u00f3n muestra que nuestra propuesta SIMD permite al compilador vectorizar eficientemente c\u00f3digos pobremente o no vectorizados autom\u00e1ticamente con el compilador Intel C\/C++.<\/jats:p>","DOI":"10.5821\/dissertation-2117-96011","type":"dissertation","created":{"date-parts":[[2023,7,19]],"date-time":"2023-07-19T02:41:29Z","timestamp":1689734489000},"approved":{"date-parts":[[2015,12,11]]},"source":"Crossref","is-referenced-by-count":0,"title":["SIMD@OpenMP : a programming model approach to leverage SIMD features"],"prefix":"10.5821","author":[{"sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Diego Luis","family":"Caballero de Gea","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"3865","container-title":[],"original-title":[],"deposited":{"date-parts":[[2026,1,28]],"date-time":"2026-01-28T06:48:32Z","timestamp":1769582912000},"score":1,"resource":{"primary":{"URL":"https:\/\/hdl.handle.net\/2117\/96011"}},"subtitle":[],"editor":[{"given":"Xavier","family":"Martorell Bofill","sequence":"first","affiliation":[],"role":[{"role":"editor","vocabulary":"crossref"}]},{"given":"Alejandro","family":"Duran Gonz\u00e1lez","sequence":"additional","affiliation":[],"role":[{"role":"editor","vocabulary":"crossref"}]}],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":0,"URL":"https:\/\/doi.org\/10.5821\/dissertation-2117-96011","relation":{},"subject":[]}}